Control Systems and Computers

https://doi.org/10.15407/csc.2019.05.012

Control Systems and Computers, 2019, Issue 5 (283), pp. 12-22.

UDC 004.274

Barkalov Oleksandr O., Doctor (Eng.), Institute of Computer Engineering and Electronics, Institute of Informatics and Electronics Zielenogorski University,  Podgorna ave., 50, Zielona Gora, 65-246, POLAND, a.barkalv@imei.uz.zgora.pl,

Titarenko Larisa A., Doctor (Eng.), Professor, Institute of Computer Engineering and Electronics, Institute of Informatics and Electronics Zielenogorski University,  Podgorna ave., 50, Zielona Gora, 65-246, POLAND,

Vizor Yaroslav Ye., PhD (Eng.), V.M. Glushkov Institute of Cybernetics of National Academy of Sciences of Ukraine, Kyiv, 03187, Glushkov ave., 40, Ukraine, E-mail: yaviz@ukr.net,

Matvienko Oleksandr V., Researcher Associate, V.M. Glushkov Institute of Cybernetics of National Academy of Sciences of Ukraine, Kyiv, 03187, Glushkov ave., 40, Ukraine, E-mail: matv@online.ua.

Synthesis of a Four-Level Schema of a Combined Automaton

Introduction. A method is proposed targeting hardware decrease in the circuit of the combined automation, implemented with LUTs and EMBs. The method is based on replacement of logical conditions and partition of the set of states by classes. Each class corresponds to a single block of the circuit. This approach leads to circuits with the regular structure and four levels of logic.

Purpose. The proposed model leads to schemes with the regular connections.  This simplifies the placement and tracing tasks when implementing the SMPA scheme.  A positive feature of the proposed model is the fact that the Clock and Start signals are associated with only one block of the circuit.  It helps to avoid the problems associated with the so-called distortion synchronization.

Results. Analysis of a special library showed that the proposed method is advisable to use for 68% of test cases.  Moreover, for 76% of the examples, the original model can be used.  For 24% of the examples, if the corresponding condition is met, only the proposed model can be used.  Our studies using Virtex-6 FPGAs showed that as the parameters R, L, N increase, the gain in equipment, speed and energy consumption for the proposed machines compared to the original ones is increased. The example is presented for using of proposed method. The conditions of its application are shown.

Conclusion. Further areas of our research are related to the development of the similar SMPA structures using: coding of sets of microoperations of the Mealy automaton; the coding of the terms of systems; and the conversion of codes of pseudo-equivalent states of the Moore automaton.

 Download full text! (In Ukrainian).

Keywords: combined automaton, synthesis, LUT, EMB, partition, FPGA.

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Received 12.09.2019