Control Systems and Computers, N1, 2017, Article 4
DOI: https://doi.org/10.15407/usim.2017.01.035
Upr. sist. maš., 2017, Issue 1 (267), pp. 35-45.
UDC 004.3
Bibilo P.N. 1, Romanov V.I.2
Constructing Compact Tests for Functional Verification of VHDL Descriptions of the Finite State Machines
1 – Doctor of technical sciences, United Institute of Informatics Problems of the National Academy of Sciences of Belarus, 6 Surganova Ulista., Minsk, 220012, Belarus, E-mail: bibilo@newman.bas-net.by,
2 – PhD of technical sciences, United Institute of Informatics Problems of the National Academy of Sciences of Belarus, 6 Surganova Ulista., Minsk, 220012, Belarus, E-mail: rom@newman.bas-net.by
Introduction. In designing digital devices, the finite state machine (FSM) model is widely used. FSM as well as other models of digital devices is represented in VHDL and Verilog languages intended to design the digital circuits in the basis of modern VLSI or user-programmable FPGA logic integrated circuits. Using VHDL-description of the finite state machines, synchronous logic circuits are synthesized based on the logic elements, called technological (target) basis or target library gates. Now, the synthesis process is automated, and the most important issue in creating the VLSI projects is the problem of verifying the original and target specifications of algorithmic descriptions of the designed digital devices and systems. Verification of the correctness of VHDL-description means checking correspondence between the composed synthesizable VHDL-description and the digital system specifications. The great advantage of FSM model is that it can be verified. Questa simulation system incorporates the tools for the functional verification of the FSM if the model is written in a certain pattern, namely, in the form of two VHDL-processes.
In the first process, the functions (transition and output) are recorded, and the other process realizes changes of the states, attaching to changes of the clock signals and the signal setting the FSM to the initial state. The first process is implemented in a combinational circuit after the circuit implementation, the second one in a memory element register. In the process of simulation, Questa simulation system allows recognizing a FSM, which is part of the project. This system identifies all passed (in particular modeling session) states of the FSM and calculates the number of passes of arcs in the transition graph of the FSM. Such tools are very useful; however, FSMs are included usually as parts of control blocks of more complicated projects. The verification of the whole project requires constructing compact functional tests for the control unit, FSM. The article considers the problem of automated construction of such tests according to the results of simulation of VHDL-description of FSM.
The FSM model and its VHDL-description are called correct if, in the FSM transition graph, there is a path from any internal state to the initial state of the FSM. Note that this condition is obligatory and always holds for the microprogram automata. The microprogram automata have been applied for a long time in the practice of engineering and are described in the present time in modern design languages. A test is an ordered sequence of sets of values of input signals fed to input ports of the FSM VHDL-model in simulation. A special test program (testbench) or a set of programs aimed at testing with different goals and different ways of organizing the tests is prepared for the simulation. The tests that allow you to check the correct functioning of the FSM model are called functional.
Problem. A correct VHDL-description of a FSM is given. It is necessary to construct a test Tsrc for functional verification by simulation that will check the performance of all the available transitions between internal states of the FSM.
Method. The selection of FSM internal states from VHDL-description and the construction of the transition graph is a nontrivial task. In fact, it is necessary to automate the process of constructing a mathematical model of FSM in form of graph of transitions by analysis VHDL-program of FSM. To solve the problem we suggest an approach for obtaining an approximate solution based on simulation of VHDL-description of the FSM on the pseudo-random test Tsrc; selection from the test Tsrc some test kits, which will be included in the target test Tres.
Conclusion. A program that allows constructing a directed graph of FSM transitions and finding coverage of all arcs on the base of the simulation results is developed. The input test kits corresponding to the arcs, which are in the coverage, make a test for the functional verification. An experimental research of the method of constructing compact tests for the verification of VHDL-models of FSM on standard examples is performed.
Received 09.12.2016
