Control Systems and Computers, N5, 2018, Article 4

DOI: https://doi.org/10.15407/usim.2018.05.038

Upr. sist. maš., 2018, Issue 5 (277), pp. 38-46.

UDC 004.274

Barkalov Aleksandr A., Doctor (Eng.),Institute of Computer Engineering and Electronics, Institute of Informatics and Electronics Zielenogorski University, ul. Podgorna, 50, Zielona Gora, 65-246, POLAND, a.barkalv@imei.uz.zgora.pl,

Titarenko Larisa A., Doctor (Eng.), Professor, Institute of Computer Engineering and Electronics, Institute of Informatics and Electronics Zielenogorski University, ul. Podgorna, 50, Zielona Gora, 65-246, POLAND,

Vizor Yaroslav Ye., PhD (Eng.), V.M. Glushkov Institute of Cybernetics of National Academy of Sciences of Ukraine, Kyiv, 03187, Glushkov ave., 40, Ukraine, E-mail: yaviz@ukr.net,

Matvienko Aleksandr V., Researcher Associate, V.M. Glushkov Institute of Cybernetics of National Academy of Sciences of Ukraine, Kyiv, 03187, Glushkov ave., 40, Ukraine, E-mail: matv@online.ua.

Encoding of collections of microoperations in combined automata

Introduction. The paper proposes a method for the synthesis of a control unit targeting the use of FPGA chips. To synthesize the final circuit, a model of a combined automaton is used. The purpose of the method is reducing the number of LUT elements.

Purpose. The purpose of the article is the development of a new method for synthesizing the scheme of a combined microprogram.

Methods. The method is based on the representation of certain microoperations of the Mile automaton by unitary codes that are generated by embedded memory block (EMB). This allows reducing the number of look-up table (LUT) elements and using only a single EMB block in the circuit of the automaton.

Results. The proposed method allows to synthesize the schemes of the combined microprogram automaton (SMPA) with one block of EMB. This is achieved by encoding sets of micro operations corresponding to the input signals of the Mill machine. To implement micro operations, LUT elements are used. The article deals with the case in which the codes of states and sets of micro operations do not affect the number of LUT elements in the automaton circuit.

Conclusion. An analysis of a specialized library showed that for 82% of all examples it is enough only a single EMB block for the implementation of a circuit of an automaton. For the remaining 18%, it is necessary use the LUT elements. Our research has shown that the proposed model of the automaton can be applied for these 18%. At the same time, the number of LUT elements decreases by an average of 48% as compared with automata with a trivial structure.

Our further research is related to the development of a method for finding micro-operations for unitary coding. The generation of these microoperations by the EMB block should lead to a minimization for the number of LUT elements in the combined automaton’s  circuit.

 Download full text! (In Russian).

Keywords: combined automaton, FPGA, LUT, EMB, encoding of microoperations, synthesis.

  1. Grout, I., 2008. Digital Systems Design with FPGAs and CPLDs. Amsterdam: Elsevier, 784 p.
  2. Maxfield, C., 2004. The Design Warrior’s Guide to FPGAs. – Orlando: Academic Press, 542 p.
  3. Garcia–Vargas, L., Senhadji–Navarro, R.M., Civit–Balcells, A. Guerra–Gutierrezz, P., 2007. “ROM–Based Finite State Machine Implementation in Low Cost FPGAs”, IEEE International Simposium on Industrial Electronics, Vigo, pp. 2342–2347.
    https://doi.org/10.1109/ISIE.2007.4374972
  4. Rawski, M., Tomaszewicz, P., Borowski, G., Luba, T., 2011. “Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks on FPGAs”, Design of Digital Systems and Devises. LNEE 70, Springer, Berlin, pp. 121–144.
    https://doi.org/10.1007/978-3-642-17545-9_5
  5. Barkalov, A., Titarenko, L., 2000. Logic Synthesis for FSM – based Control Units, Berlin: Springer, 233 p.
  6. Baranov, S., 1994. Logic Synthesis for Control Automata, Dordrecht: Kluwer Academic Publishers, 312 p.
    https://doi.org/10.1007/978-1-4615-2692-6
  7. Barkalov, A.A., Titarenko, L.A., Vizor, Ya.Ye., Matvienko, A.V., Gorina, V.V., 2016. “Synthesis of Combined Finite State Machine with FPGAs”, Upravlausie sistemy i masiny, 2016, 3, pp. 16–22. (In Russian).
  8. Skliarova, I., Sklyarov, V., Sudnitson, A., 2012. Design of FPGA–based circuits using Hierarchical Finite State Machines. Tallinn: TUT Press, 240 p.
  9. Barkalov, A.A., Titarenko, L.A., Vizor, Ya.Ye., Matvienko, A.V., 2015. “Realizatsiya skhemy sovmeshchennogo mikroprogrammnogo avtomata v bazise FPGA”. Problemy informatyzatsiyi ta upravlinnya: Zb. naukov. Prats, Natsionalʹnyy aviatsiynyy universytet, K., 3(51), pp. 5–8. (In Russian).
  10. Yang, S., 1991. Logic Synthesis and optimization benchmarks user guide. Microelectronics Center of North Carolina, 43 p.

Received 27.11.2018